This work studies how a real-time operating system behaves on the open RISC-V instruction set. The public repository combines a theoretical foundation with a reproducible QEMU setup, task-scheduling experiments, functional checks, and statistical analysis of latency, worst-case execution time, and jitter.
The hardware side follows the same question into a Tang Nano 9K FPGA and PicoRV32-based implementation attempt. The useful result is not a claim that the hardware path is finished; it is a record of the integration challenges and the measurements needed to reason about RTOS behavior across simulation and hardware.